features fast access time : 55/70ns low power consumption: operating current : 45/ 30ma (typ.) standby current : 4 a (typ.) sl-version single 2.7v ~ 3.6v power supply all inputs and outputs ttl compatible fully static operation tri-state output data byte control : lb# (dq0 ~ dq7) ub# ( dq 8 ~ dq15) data retention voltage : 1.2v (min.) lead free and green package available package : 48-ball 6mm x 8mm tfbga general description the as6c1616 is a 16,777,216-bit low pow e r cmos static random access memory organized as 1,048,576 words by 16 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the as6c1616 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. the as6c16 16 operates from a singlepower supply of 2.7v ~ 3.6v and all inputs and outputs are fully ttl compatible product family power d issipation product family operating temperature vcc range speed standby(i sb1, typ.) operating (icc,typ.) as6c161 6(i) -40 ~ 85 c 2.7 ~ 3.6v 55/ 70ns 4a 45/30ma functional block diagram control circuit decoder 1024kx16 memor y array co lu mn i/o a0-a19 vcc vss dq8-dq15 upp er byte dq 0- dq7 low er b yte i/o data circuit ce2 we# oe# lb# ub# ce# pin description symbol description a0 - a19 address inputs dq0 C dq15 data inputs/outputs ce#, ce2 chip enable input we# write enable input oe# lb# ub# v cc power supply v ss ground output enable input lower byte control upper byte control o 512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 as6c1616 february/2009, v 1.a alliance memory inc. page 1 of 11
pin configuration tfbga a19 a3 11a 9a 01a a0 a14 a8 nc we# dq9 dq14 dq15 a18 vss ce2 a13 dq8 vcc vcc dq7 a15 vss ce# lb# dq6 dq2 dq0 a2 oe# a1 5a 6a a4 ub# 123 4 5 6 h g c d e f a b a12 nc a17 a7 a16 dq10 dq11 dq12 dq13 dq5 dq4 dq3 dq1 absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 4.6 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a -40 to 85(i grade) storage temperature t st g -65 to 150 powe r di ss ipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) t so ld er 260 *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to t he device. this is a stress rating only and functional operation of the device or any other conditions above t hose indicated in the operational sections of this specificat ion is not implied. exposure t o the absolute maximum rating conditions for extended period may af fect device reliabi lity. 512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 february/2009, v 1.a alliance memory inc. page 2 of 11 as6c1616
t ru th table i/o operation mode ce# ce2 oe# we# lb# ub# dq0-dq7 dq8-dq15 supply current standby h x x x l x x x x x x x x x h x x h high C z high C z high C z high C z high C z high C z i sb ,i sb1 output disable l l h h h h h h l x x l high C z high C z high C z high C z i cc ,i cc 1 re ad l l l h h h l l l h h h l h l h l l d out high C z d out high C z d out d out i cc ,i cc 1 write l l l h h h x x x l l l l h l h l l d in high C z d in high C z d in d in i cc ,i cc 1 note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. *4 max. unit supply voltage v cc 2.7 3.0 3.6 v input high voltage v ih *1 2.2 - v cc +0 .3 v input low voltage v il *2 - 0.2 - 0.6 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v ou t R v ss output disabled - 1 - 1 a output high voltage v oh i oh = -1ma 2.2 2.7 - v output low voltage v ol i ol = 2ma - - 0.4 v -55 45 60 ma i cc cycle time = min. ce# = v il an d ce2 = v ih i i/ o = 0m a -70 - 30 45 ma other pins at v il or v ih average operating power supply current i cc 1 cycle time = 1 s ce# Q 0.2v and ce2 R v cc -0.2v i i/ o = 0m a other pins at 0.2v or v cc -0.2v - 8 16 ma i sb ce# = v ih or ce2 = v il other pins at v il or v ih - 0.3 2 ma -sli - 6 40 a standby power supply current i sb1 ce# v R cc -0.2v or ce2 Q 0.2v other pins at 0.2v or v cc -0.2v notes: 1. v ih (max) = v cc + 3.0v f or pulse width less t han 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guara nt eed or tested. typical values are measured at v cc = v cc (typ.) and t a = 25 512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 february/2009, v 1.a alliance memory inc. page 3 of 11 as6c1616
timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc prev iou s data valid read cycle 2 (ce# and ce2 and oe# controlled) (1,3,4,5) dout da ta valid hig h-z hi gh -z t clz t olz t chz t ohz t oh oe# t oe lb#,ub# t bhz t ace t ba t blz ce# t aa address t rc ce2 note s : 1.w e#is high f or read cycle. 2.device i s c ontinuously selected oe# = low, ce# = low, ce2 = high, lb# or ub# = low . 3.address must be v alid prior t o or c oincident with ce# = low, ce2 = high , lb# or ub# = low transition; otherwise t aa is the limit ing parameter. 4.t clz , t blz, t olz , t chz, t bhz and t ohz are speci ed with c l = 5pf. transition is measured 500mv fro m st eady s tate. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less t han t blz , t ohz is less than t ol z. 512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 february/2009, v 1.a alliance memory inc. page 5 of 11 as6c1616
write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow lb#,ub# t bw ce# t aw address t wc ce2 write cycle 2 (ce# and ce2 controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw t wp t bw ce# address t wr t as t aw t wc ce2 512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 february/2009, v 1.a alliance memory inc. page 6 of 11 as6c1616
write cycle 3 (lb# ,ub# contr o ll ed) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw t as t wp t bw ce# address t wr t aw t wc ce2 note s : 1.w e#,ce#, lb#, ub# must be high or ce2 must be low during all address t ransitions. 2.a write occurs during the overlap of a low ce#, high ce2, low we#, lb# or ub# = low. 3.during a we# con tr olled write c ycle with oe # low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the outpu t s tate, and input signals must not be applied. 5.if the ce#, lb#, ub# low transition and ce2 high transition o ccurs s imultaneously with or afte r we # low transition, t he outputs remain in a high impedance s tate. 6.t ow and t whz are s pecified with c l = 5pf. transition is measured 500mv from st eady s tate. 512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 february/2009, v 1.a alliance memory inc. page 7 of 11 as6c1616
data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v or ce2 Q 0.2v 1.2 - 3.6 v -sli - 4 40 a data retention current i dr v cc = 1.2v ce# R v cc -0.2v or ce2 Q 0.2v other pins at 0.2v or v cc -0.2v chip disable to data retention time t cdr see data retention waveform s (below) 0 - - ns re co very time t r t rc * - - ns t rc * = re ad cycle ti me data retention waveform low vcc data retention waveform (1) (ce# contro ll ed) vcc ce# v dr R 1.2v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vc c( min.) low vcc data retention waveform (2) (ce2 contro ll ed ) vcc ce2 v dr R 1. 2v ce2 Q 0.2v vcc(min.) v il t r t cdr v il vc c( mi n. ) low vcc data retention waveform (3) (lb#, ub# c o ntrol l ed ) vcc lb#,ub# v dr R 1. 2v lb#,ub# v R cc-0 .2v vcc(min.) v ih t r t cdr v ih vc c( mi n. ) 512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 february/2009, v 1.a alliance memory inc. page 8 of 11 as6c1616
package outline dimension 48-ball 6mm 8mm tfbga package outline dimension 512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 february/2009, v 1.a alliance memory inc. page 9 of 11 as6c1616
february 2009 as6c 1616 1024k x 16 bit low power cmos sram february /2009, v1.a alliance memory inc. page 1 0 of 1 1 ordering information alliance organization vcc range package operating temp speed ns as6c 16 16 - 70b in 1024 k x 16 2.7 - 3.6v 4 8ball tfbga industrial ~ - 40 c C 85 c) 70 as6c 16 16 - 55 b in 1024 k x 16 2.7 - 3.6v 4 8ball tfbga industrial ~ - 40 c C 85 c) 55 part numbering system as6c 16 16 - 70 x x n low power s ram prefix device number 16 = 16 m 16 = x16 access time package option 48ball tfbga temperature ran ge i = industrial ( - 40 to + 85 c) n = lead free rohs compliant part
512k x 8 bi t low power cmos sram january 2007 1024k x 16 bit low power cmos sram february 2009 february/2009, v 1.a alliance memory inc. page 11 of 11 as6c1616 allian ce memory, in c 511 taylor way, san carlos, ca 94070, usa phone: 650-610-6800 fax: 650-620-9211 www.alliancememory.com ? copyright 2009 a llian ce memory, inc. all rights reserved. our three-point lo go, our nam e and inte lliwa t are trademarks or reg ist ered trademarks of a llian ce. all other brand and product name s ma y be the trademarks of their respectve compani es . allian ce reserves the right to make changes to thi s document and it s products at any tme wit hou t not ce. alli anc e assu me s no res pons ibili ty for any errors that ma y app ea r in thi s document. the data contained herein represents a llian ce's best data and/or estmates at th e tme of issuance. a llian ce reserve s the right to change or correc t thi s data at any t me , wit hou t notce. if the product described herein is und er deve lo pment, sig ni?cant chan ge s to these spec i?catons are possible. th e informat on in thi s product data shee t is intended to be ge ne ra l de scriptve inform at on for pot e ntal customers and us ers , and is not intended to operate as , or provide any guarantee or warrantee to any u se r or customer. a llia nc e doe s not assume any res pons ibili ty or liabi lity arising ou t of the applicat on or us e of any product described herein, and di sclaims any ex pres s or impli ed warrantes related to the sale and/or us e of allian ce produ ct s including liabili ty or warrantes related to ?tness for a p artcul ar purpose, merchanta bili ty, or infrin ge ment of any inte lle ctua l property rights, ex cept as ex pre ss agre ed to in allian ce's terms and conditons of sal e (w hi ch are available from allian ce). al l sales of allian ce products are ma de excl usi ve ly acc ordin g to a llian ce's terms and conditons of sale. the purchase of products from allian ce doe s not convey a li cense und er any patent rights, cop yrights; mask wor ks rights, trademarks, or any other inte lle ctua l property rights of allian ce or third partes. a llian ce doe s not autho rize it s products for us e as cri t cal components in lif e-sup portng sy stem s where a malfuncton or failu re ma y reasonably be expected to result in signi? cant injury to the us er , and the inclusio n of allian ce produ ct s in su ch lif e-sup portng system s impli es that the manufacturer assum es all risk of su ch us e and agre es to indemnify a llian ce against all cla ims arising from such us e. copyright ? alliance memory all ri gh ts re served
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